As the channel length of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) continues to scale, a series of effects that can be neglected in the long-channel model of MOSFETs become more significant, and even become the dominant factor that affects the performance. Such phenomenon is generally referred to as short channel effect. Short channel effect leads to the deterioration of the electrical properties of the device, e.g., leading to problems such as reduction of the gate threshold voltage, increase in power consumption, and signal-to-noise ratio (SNR) decline.
In order to improve short channel effect, the dominant idea in the industry is to improve the conventional planar-type device technology, to reduce the thickness of the channel region, and to eliminate the neutral layer that depletes the bottom of the layer in the channel, so that the depletion layer in the channel can fill the entire channel region, namely, the so-called Fully Depleted (FD) device, while conventional planar-type devices are Partially Depleted (PD) devices.
However, the manufacture of a fully depleted device requires the thickness of the silicon layer in the channel to be quite small. Traditional manufacturing processes, especially traditional bulk silicon-based processes can hardly manufacture structures that meet the requirements, or the cost is too high. Even for the emerging SOI (silicon on insulator) technology, the thickness of the channel silicon layer is also difficult to be controlled at a thin level. The focus of R & D has been shifted to 3D device structures to achieve a fully depleted device.
3D device structures (which are also referred to as vertical-type devices in some references) refer to structures where the cross sections of the source/drain regions and the gate of the device are not within the same plane, and substantially belong to FinFET (fin field effect transistor) structures.
After shifting to 3D device structures, since the channel region is separated from these structures rather than included in the bulk silicon or SOI, it is possible to manufacture a fully depleted channel with a very small thickness by means such as etching.
The 3D semiconductor device that has been proposed is illustrated in FIG. 1. The semiconductor device comprises: a fin 020 on an insulating layer 010; source/drain regions 030 connected to an opposite first side 022 in the fin 020; a gate 040 located on a second side 024 adjacent to the first side 022 in the fin 020 (the gate dielectric layer and the work function metal layer sandwiched between the gate 040 and the fin 020 are not shown in the figure). In order to reduce the resistance of the source/drain regions, the edge portion of the source/drain regions 030 can be extended, i.e., the width of the source/drain regions 030 (along the xx′ direction) is greater than the thickness of the fin 020. The 22 nm technology node and below is expected to be applied to the 3D semiconductor structures. As the device dimension further shrinks, the short channel effect of 3D semiconductor devices will also become a major factor that affects the device performance.
As a 3D semiconductor device, nanowire MOSFET can control the short channel effect effectively and has a low random dopant fluctuation, and therefore is promising for the future further scaled-down MOSFET. However, the nanowire device manufacturing process is very difficult currently.